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vishay siliconix SIS427EDN document number: 62856 s13-1164-rev. a, 13-may-13 www.vishay.com 1 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com p-channel 30-v (d-s) mosfet features ? trenchfet ? power mosfet ?100 % r g and uis tested ? typical esd performance: 2500 v (hbm) ? material categorization: for definitions of compliance please see www.vishay.com/doc?99912 applications ? notebook battery charging ? notebook adapter switch ? load switch/power management for mobile computing notes: a. surface mounted on 1" x 1" fr4 board. b. t = 10 s. c. maximum under steady stat e conditions is 81 c/w. d. package limited. e. see solder profile ( www.vishay.com/doc?73257 ). the powerpak 1212-8 is a leadless package. the end of the lead terminal is exposed copper (not plated) as a result of the si ngulation process in manufactu ring. a solder fillet at the exposed copper tip cannot b e guaranteed and is not required to ensure adequate bottom side solder interconnection. f. rework conditions: manual sol dering with a soldering iron is not recommended for leadless components. g. based on t c = 25 c. product summary v ds (v) r ds(on) ( ? ) max. i d (a) d, g q g (typ.) - 30 0.0106 at v gs = - 10 v - 50 d 22.6 nc 0.0160 at v gs = - 6 v - 42.1 0.0213 at v gs = - 4.5 v - 31.3 1 2 3 4 5 6 7 8 s s s g d d d d 3.30 mm 3.30 mm powerpak ? 1212-8 bottom view ordering information: SIS427EDN-t1-ge3 (lead (pb)-free and halogen-free) s g d p-channel mosfet absolute maximum ratings (t a = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds - 30 v gate-source voltage v gs 25 continuous drain current (t j = 150 c) t c = 25 c i d - 50 d a t c = 70 c - 44.3 t a = 25 c - 15 a, b t a = 70 c - 12 a, b pulsed drain current (t = 100 s) i dm - 110 continuous source-drain diode current t c = 25 c i s - 43 t a = 25 c - 3.1 a, b avalanche current l = 0.1 mh i as - 25 single-pulse avalanche energy e as 31.25 mj maximum power dissipation t c = 25 c p d 52 w t c = 70 c 33 t a = 25 c 3.7 a, b t a = 70 c 2.4 a, b operating junction and storage temperature range t j , t stg - 55 to 150 c soldering recommendations (peak temperature) e, f 260 thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient a, c t ?? 10 s r thja 26 33 c/w maximum junction-to-case steady state r thjc 1.9 2.4
vishay siliconix SIS427EDN www.vishay.com 2 document number: 62856 s13-1164-rev. a, 13-may-13 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com notes: a. pulse test; pulse width ? 300 s, duty cycle ? 2 %. b. guaranteed by design, not subject to production testing. c. t = 100 s stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications (t j = 25 c, unless otherwise noted) parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = - 250 a - 30 v v ds temperature coefficient ? v ds /t j i d = - 250 a - 21 mv/c v gs(th) temperature coefficient ? v gs(th) /t j 4.8 gate-source threshold voltage v gs(th) v ds = v gs , i d = - 250 a - 1.2 - 2.5 v gate-source leakage i gss v ds = 0 v, v gs = 25 v 250 a v ds = 0 v, v gs = 20 v 10 zero gate voltage drain current i dss v ds = - 30 v, v gs = 0 v - 1 v ds = - 30 v, v gs = 0 v, t j = 55 c - 5 on-state drain current a i d(on) v ds ? - 10 v, v gs = - 10 v - 30 a drain-source on-state resistance a r ds(on) v gs = - 10 v, i d = - 11 a 0.0088 0.0106 ? v gs = - 6 v, i d = - 7 a 0.0133 0.0160 v gs = - 4.5 v, i d = - 7 a 0.0177 0.0213 forward transconductance a g fs v ds = - 15 v, i d = - 11 a 32 s dynamic b input capacitance c iss v ds = - 15 v, v gs = 0 v, f = 1 mhz 1930 pf output capacitance c oss 410 reverse transfer capacitance c rss 355 total gate charge q g v ds = - 15 v, v gs = - 10 v, i d = - 15 a 43.5 66 nc v ds = - 15 v, v gs = - 4.5 v, i d = - 15 a 22.6 34 gate-source charge q gs 6 gate-drain charge q gd 11 gate resistance r g f = 1 mhz 0.2 1.2 2.4 ? tu r n - o n d e l ay t i m e t d(on) v dd = - 15 v, r l = 1.25 ? i d ? - 12 a, v gen = - 10 v, r g = 1 ? 11 22 ns rise time t r 13 20 turn-off delaytime t d(off) 26 40 fall time t f 714 tu r n - o n d e l ay t i m e t d(on) v dd = - 15 v, r l = 1.25 ? i d ? - 12 a, v gen = - 4.5 v, r g = 1 ? 45 68 rise time t r 40 60 turn-off delaytime t d(off) 28 42 fall time t f 12 22 drain-source body diode characteristics continous source-drain diode current i s t c = 25 c - 50 a pulse diode forward current c i sm - 110 body diode voltage v sd i s = - 12 a, v gs = 0 v - 0.8 - 1.2 v body diode reverse recovery time t rr i f = - 12 a, di/dt = 100 a/s, t j = 25 c 22 33 ns body diode reverse recovery charge q rr 14 21 nc reverse recovery fall time t a 13 ns reverse recovery rise time t b 9
vishay siliconix SIS427EDN document number: 62856 s13-1164-rev. a, 13-may-13 www.vishay.com 3 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com typical characteristics (25 c, unless otherwise noted) gate source voltage vs. gate current output characteristics on-resistance vs. drain current 0.000 0.010 0.020 0.030 0.040 0.050 0 6 12 18 24 30 i gss - gate current (ma) v gs - gate-source voltage (v) t j = 25 c 0 10 20 30 40 50 0 1 2 3 4 5 i d - drain current (a) v ds - drain-to-source voltage (v) v gs = 4 v v gs = 10 v thru 4.5 v v gs = 3 v 0 0.006 0.012 0.018 0.024 0.03 0 15 30 45 60 r ds(on) - on-resistance () i d - drain current (a) v gs = 4.5 v v gs = 6 v v gs = 10 v gate source voltage vs. gate current transfer characteristics capacitance 10 -3 10 -4 10 -5 10 -6 10 -7 10 -8 0 11 22 33 44 i gss - gate current (a) v gs - gate-to-source voltage (v) t j = 150 c t j = 25 c 0 1 2 3 4 5 0 0.6 1.2 1.8 2.4 3 i d - drain current (a) v gs - gate-to-source voltage (v) t c = 25 c t c = 125 c t c = - 55 c 0 600 1200 1800 2400 3000 0 6 12 18 24 30 c - capacitance (pf) v ds - drain-to-source voltage (v) c iss c oss c rss
vishay siliconix SIS427EDN www.vishay.com 4 document number: 62856 s13-1164-rev. a, 13-may-13 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com typical characteristics (25 c, unless otherwise noted) gate charge source-drain diode forward voltage on-resistance vs. junction temperature 0 2 4 6 8 10 0 10 20 30 40 50 v gs - gate-to-source voltage (v) q g - total gate charge (nc) v ds = 24 v v ds = 15 v v ds = 8 v i d = 15 a 0.1 1 10 100 0.0 0.3 0.6 0.9 1.2 i s - source current (a) v sd - source-to-drain voltage (v) t j = 150 c t j = 25 c 0.65 0.85 1.05 1.25 1.45 1.65 - 50 - 25 0 25 50 75 100 125 150 r ds(on) - on-resistance (normalized) t j - junction temperature ( c) i d = 11a v gs = 10 v, 6 v v gs = 4.5 v , threshold voltage on-resistance vs. gate-to-source voltage single pulse power, junction-to-ambient 1.05 1.25 1.45 1.65 1.85 2.05 - 50 - 25 0 25 50 75 100 125 150 v gs(th) (v) t j - temperature ( c) i d = 250 a 0.000 0.006 0.012 0.018 0.024 0.030 2 4 6 8 10 r ds(on) - on-resistance () v gs - gate-to-source voltage (v) t j = 125 c t j = 25 c i d = 11 a 0 10 20 30 40 50 0.01 0.1 1 10 100 1000 time (s) po w er ( w )
vishay siliconix SIS427EDN document number: 62856 s13-1164-rev. a, 13-may-13 www.vishay.com 5 mosfet typical characteristics (25 c, unless otherwise noted) * the power dissipation p d is based on t j(max.) = 150 c, using junction-to-cas e thermal resistance, and is mo re useful in settling the upper dissipation limit for cases where additional heatsinking is used. it is used to determine the current rating, when this rating falls below the package limit. safe operating area current derating* 0.001 0.01 0.1 1 10 100 1000 0.1 1 10 100 i d - drain current (a) v ds - drain-to-source voltage (v) * v gs > minimum v gs at which r ds(on) is specified 100 ms limited by r ds(on) * 1 ms t a = 25 c single pulse bvdss limited 10 ms 100 s 10s, 1 s dc, 0 16 32 48 64 0 25 50 75 100 125 150 i d - drain current (a) t c - case temperature ( c) power derating, junction-to-case power derating, junction-to-ambient 0 16 32 48 64 0 25 50 75 100 125 150 power (w) t c - case temperature ( c) 0.0 0.5 1.0 1.5 2.0 0 25 50 75 100 125 150 power (w) t a - ambient temperature ( c)
vishay siliconix SIS427EDN www.vishay.com 6 document number: 62856 s13-1164-rev. a, 13-may-13 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com typical characteristics (25 c, unless otherwise noted) vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?62856 . normalized thermal transient im pedance, junction-to-ambient 10 -3 10 -2 1 10 1000 10 -1 10 -4 100 0.2 0.1 0.05 s qu are w a v ep u lse d u ration (s) n ormalized effecti v e transient thermal impedance 1 0.1 0.01 single p u lse t 1 t 2 n otes: p dm 1. d u ty cycle, d = 2. per unit base = r thja = 8 1 c/ w 3. t jm -t a =p dm z thja (t) t 1 t 2 4. s u rface mo u nted d u ty cycle = 0.5 0.02 normalized thermal transient impedance, junction-to-case 1 0.1 0.01 0.2 d u ty cycle = 0.5 s qu are w a v ep u lse d u ration (s) n ormalized effecti v e transient thermal impedance single p u lse 0.1 10 -3 10 -2 1 10 -1 10 -4 0.02 0.05
package information www.vishay.com vishay siliconix revison: 09-jan-17 1 document number: 71656 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 powerpak ? 1212-8, (single / dual) dim. millimeters inches min. nom. max. min. nom. max. a 0.97 1.04 1.12 0.038 0.041 0.044 a1 0.00 - 0.05 0.000 - 0.002 b 0.23 0.30 0.41 0.009 0.012 0.016 c 0.23 0.28 0.33 0.009 0.011 0.013 d 3.20 3.30 3.40 0.126 0.130 0.134 d1 2.95 3.05 3.15 0.116 0.120 0.124 d2 1.98 2.11 2.24 0.078 0.083 0.088 d3 0.48 - 0.89 0.019 - 0.035 d4 0.47 typ. 0.0185 typ d5 2.3 typ. 0.090 typ e 3.20 3.30 3.40 0.126 0.130 0.134 e1 2.95 3.05 3.15 0.116 0.120 0.124 e2 1.47 1.60 1.73 0.058 0.063 0.068 e3 1.75 1.85 1.98 0.069 0.073 0.078 e4 0.034 typ. 0.013 typ. e 0.65 bsc 0.026 bsc k 0.86 typ. 0.034 typ. k1 0.35 - - 0.014 - - h 0.30 0.41 0.51 0.012 0.016 0.020 l 0.30 0.43 0.56 0.012 0.017 0.022 l1 0.06 0.13 0.20 0.002 0.005 0.008 ? 0 - 12 0 - 12 w 0.15 0.25 0.36 0.006 0.010 0.014 m 0.125 typ. 0.005 typ. ecn: s16-2667-rev. m, 09-jan-17 dwg: 5882 notes 1. inch will govern 2 dimen s ion s exclu s ive of mold gate burr s 3. dimen s ion s exclu s ive of mold fla s h and cutting burr s back s ide view of s ingle pad back s ide view of dual pad detail z d1 d2 d1 e1 c a 5 4 1 8 d2 4 3 h 2 1 e b e2 l b d3(2x) 4 3 2 1 a1 z k k1 w m d4 e3 e4 d5 k h e4 e2 l d2 d4 e3 d5 l1 2 2 d e h
vishay siliconix an822 document number 71681 03-mar-06 www.vishay.com 1 powerpak ? 1212 mounting and thermal considerations johnson zhao mosfets for switching applic ations are now available with die on resistances around 1 m and with the capability to handle 85 a. while these die capabilities represent a major advance over what was available just a few years ago, it is important for power mosfet packaging technology to keep pace. it should be obvi- ous that degradation of a high performance die by the package is undesirable. powerpak is a new package technology that addresses these issues. the powerpak 1212-8 provides ultra-low thermal impedance in a small package that is ideal for space-constrained applications. in this application note, the powerpak 1212-8?s construction is described. fo llowing this, mounting information is presented. finally, thermal and electrical performance is discussed. the powerpak package the powerpak 1212-8 package (figure 1) is a deriva- tive of powerpak so-8. it utilizes the same packaging technology, maximizing the die area. the bottom of the die attach pad is exposed to provide a direct, low resis- tance thermal path to the substrate the device is mounted on. the powerpak 1212-8 thus translates the benefits of the powe rpak so-8 into a smaller package, with the same level of thermal performance. (please refer to application note ?powerpak so-8 mounting and thermal considerations.?) the powerpak 1212-8 has a footprint area compara- ble to tsop-6. it is over 40 % smaller than standard tssop-8. its die capacity is more than twice the size of the standard tsop-6?s. it has thermal performance an order of magnitude better than the so-8, and 20 times better than tssop-8. its thermal performance is better than all current smt packages in the market. it will take the advant age of any pc board heat sink capability. bringing the junc tion temperature down also increases the die efficiency by around 20 % compared with tssop-8. for applications where bigger pack- ages are typically required solely for thermal consider- ation, the powerpak 1212- 8 is a good option. both the single and dual po werpak 1212-8 utilize the same pin-outs as the single and dual powerpak so-8. the low 1.05 mm powerpak height profile makes both versions an excellent choice for applications with space constraints. powerpak 1212 single mounting to take the advantage of th e single powerpak 1212-8?s thermal performance see application note 826, recommended minimum pad patterns with outline drawing access for vishay siliconix mosfets. click on the powerpak 1212-8 single in the index of this document. in this figure, the drain land pattern is given to make full contact to the drain pa d on the powerpak package. this land pattern can be extended to the left, right, and top of the drawn pattern. this ex tension will serve to increase the heat dissipation by decreasing the ther- mal resistance from the foot of the powerpak to the pc board and therefore to the ambient. note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-to- ambient thermal resistance. under specific conditions of board configuration, copper weight, and layer stack, experiments have found that adding copper beyond an area of about 0.3 to 0.5 in 2 of will yield little improve- ment in thermal performance. figure 1. powerpak 1212 devices
www.vishay.com 2 document number 71681 03-mar-06 vishay siliconix an822 powerpak 1212 dual to take the advantage of the dual powe rpak 1212-8?s thermal performance, the minimum recommended land pattern can be found in application note 826, recommended minimum pad patterns with outline drawing access for vishay siliconix mosfets . click on the powerpak 1212-8 dual in the index of this doc- ument. the gap between the two drain pads is 10 mils. this matches the spacing of the two drain pads on the pow- erpak 1212-8 dual package. this land pattern can be extended to the left, right, and top of the drawn pattern. this extension will serve to increase the heat dissipation by decreasing the ther- mal resistance from the foot of the powerpak to the pc board and therefore to the ambient. note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-to- ambient thermal resistance. under specific conditions of board configuration, copper weight, and layer stack, experiments have found that adding copper beyond an area of about 0.3 to 0.5 in 2 of will yield little improve- ment in thermal performance. reflow soldering vishay siliconix surface- mount packages meet solder reflow reliability requirement s. devices are subjected to solder reflow as a preconditioning test and are then reliability-tested using tem perature cycle, bias humid- ity, hast, or pressure pot. the solder reflow tempera- ture profile used, and the temperatures and time duration, are shown in figures 2 and 3. for the lead (pb)-free solder profile, see http://www.vishay.com/ doc?73257. ramp-up rate + 6 c /second maximum temperature at 155 15 c 120 seconds maximum temperature above 180 c 70 - 180 seconds maximum temperature 240 + 5/- 0 c time at maximum temperature 20 - 40 seconds ramp-down rate + 6 c/second maximum figure 2. solder reflow temperature profile figure 3. solder reflow temperatures and time durations 210 - 220 c 3 c/s (max) 4 c/s (max) 10 s (max) 1 8 3 c 50 s (max) reflo w zone 60 s (min) pre-heating zone 3 c/s (max) 140 - 170 c maxim u m peak temperat u re at 240 c is allo w ed.
vishay siliconix an822 document number 71681 03-mar-06 www.vishay.com 3 thermal performance introduction a basic measure of a device?s thermal performance is the junction-to-case thermal resistance, r jc, or the junction to- foot thermal resistance, r jf. this parameter is measured for the device mounted to an infinite heat sink and is therefore a char acterization of the device only, in other words, independent of the properties of the object to which the device is mounted. table 1 shows a comparison of the power pak 1212-8, powerpak so-8, standard tssop-8 and so-8 equivalent steady state performance. by minimizing the junction-to- foot thermal resistance, the mosfet die temperature is very close to the tempera- ture of the pc board. consider four devices mounted on a pc board with a board temperature of 45 c (figure 4) . suppose each device is dissipating 2 w. using the junc- tion-to-foot thermal resistance characteristics of the powerpak 1212-8 and the other smt packages, die temperatures are determined to be 49.8 c for the pow- erpak 1212-8, 85 c for the standard so-8, 149 c for standard tssop-8, and 125 c for tsop-6. this is a 4.8 c rise above the board temperature for the power- pak 1212-8, and over 40 c for other smt packages. a 4.8 c rise has minimal effect on r ds(on) whereas a rise of over 40 c will cause an increase in r ds(on) as high as 20 %. spreading copper designers add additional copper, spreading copper, to the drain pad to aid in conducting heat from a device. it is helpful to have some in formation about the thermal performance for a given area of spreading copper. figure 5 and figure 6 show the thermal resistance of a powerpak 1212-8 single and dual devices mounted on a 2-in. x 2-in., four-layer fr-4 pc boards. the two inter- nal layers and the backside la yer are solid copper. the internal layers were chosen as solid copper to model the large power and ground planes common in many appli- cations. the top layer was cut back to a smaller area and at each step junction-to-ambient thermal resistance measurements were taken. the results indicate that an area above 0.2 to 0.3 square inches of spreading copper gives no additional thermal performance improvement. a subsequent experiment was run where the copper on the back-side was reduced, first to 50 % in stripes to mimic circuit traces, and then totally removed. no signif- icant effect was observed. table 1: eqivalent steady state performance package so-8 tssop-8 tsop-8 ppak 1212 ppak so-8 configuration single dual single dual single dual single dual single dual thermal resiatance r thjc (c/w) 20 40 52 83 40 90 2.4 5.5 1.8 5.5 figure 4. temperature of devices on a pc board 2.4 c/ w 49. 8 c po w erpak 1212 20 c/ w 8 5 c standard so- 8 pc board at 45 c 52 c/ w 149 c standard tssop- 8 40 c/ w 125 c tsop-6
www.vishay.com 4 document number 71681 03-mar-06 vishay siliconix an822 conclusions as a derivative of the powerpak so-8, the powerpak 1212-8 uses the same packaging technology and has been shown to have the same level of thermal perfor- mance while having a footprint that is more than 40 % smaller than the standard tssop-8. recommended powerpak 1212 -8 land patterns are provided to aid in pc board layout for designs using this new package. the powerpak 1212-8 combines small size with attrac- tive thermal characteristics. by minimizing the thermal rise above the boa rd temperature, powerpak simplifies thermal design considerations, allows the device to run cooler, keeps r ds(on) low, and permits the device to handle more current than a same- or larger-size mos- fet die in the standard tssop-8 or so-8 packages. figure 5. spreading copper - si7401dn 45 55 65 75 8 5 95 105 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 r a j h t (c/ w ) spreading copper (s q . in.) 100 % 50 % 0 % figure 6. spreading copper - junction-to-ambient performance r a j (c/ w ) h t 50 60 70 8 0 90 100 110 120 130 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 spreading copper (s q . in.) 100 % 0 % 50 %
application note 826 vishay siliconix document number: 72597 www.vishay.com revision: 21-jan-08 7 application note recommended minimum pads for powerpak ? 1212-8 single 0.088 (2.235) recommended mi nimum pads dimensions in inches/(mm) 0.152 (3.860) 0.094 (2.390) 0.039 (0.990) 0.068 (1.725) 0.010 (0.255) 0.016 (0.405) 0.026 (0.660) 0.025 (0.635) 0.030 (0.760) return to index return to index
legal disclaimer notice www.vishay.com vishay revision: 13-jun-16 1 document number: 91000 disclaimer ? all product, product specifications and data ar e subject to change with out notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of th e products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product , (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all implied warranties, includ ing warranties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain types of applicatio ns are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular applic ation. it is the customers responsibility to validate tha t a particular product with the prope rties described in the product sp ecification is suitable for use in a particular application. parameters provided in datasheets and / or specifications may vary in different ap plications and perfor mance may vary over time. all operating parameters, including ty pical parameters, must be va lidated for each customer application by the customer s technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product could result in personal injury or death. customers using or selling vishay product s not expressly indicated for use in such applications do so at their own risk. please contact authorized vishay personnel to obtain writ ten terms and conditions rega rding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

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